The wafer level chip size packaging (WLCSP) technology is a technology where a full wafer is packaged and tested, and then is cut to acquire individual finished chip packages, the packaged chip package being the same size as a die.
The wafer level chip size packaging technology changes the conventional packaging manners such as the packaging manner of the ceramic leadless chip carrier, the packaging manner of the organic leadless chip carrier and the packaging manner of the digital camera module, and meets the increasing market demand for lighter, smaller, shorter, thinner and lower-priced microelectronic products. A chip packaged using the wafer level chip size packaging technology is highly miniaturized, and the cost of the chip is dramatically reduced with a decrease in the chip size and an increase in the wafer size. The wafer level chip size packaging technology combines IC design, wafer fabrication, package test, and substrate fabrication together, and is an on-going concern as well as a future development trend in the current packaging field.
In the wafer level packaging technology, especially in the case of packaging an image sensing chip, an upper cover substrate is generally covered on a surface of the semiconductor wafer on which devices are formed, in order to protect the devices from damage and pollution during packaging.
Reference is made to FIG. 1, which is a schematic cross-sectional structural diagram of a wafer level chip packaging structure. The wafer level chip packaging structure includes: a substrate 10, where a sensing region 20 is formed on the substrate 10, contact pads 21 are formed on the substrate 10 on two sides of the sensing device, a through hole is formed on another surface of the substrate 10 which is opposite to the sensing region 20, the contact pad 21 is exposed by the through hole, an insulation layer 11 is formed on a sidewall of the through hole and the surface of the substrate 10, a line layer 12 is formed on the surface of the contact pad 21 and a part of a surface of the insulation layer 11, the line layer 12 and the insulation layer 11 are covered by a solder mask 13 having an opening, and a solder ball 14 which is connected with the line layer 12 is disposed at the opening.
The surface of the substrate 10 provided with the sensing region 20 is covered by an upper cover substrate 30. A cavity wall 31 is disposed between the upper cover substrate 30 and the surface of the substrate 10. A cavity is formed between the cavity wall 31, the upper cover substrate 30 and the substrate 10, and the sensing region 20 is located in the cavity to protect the device from pollution and damage.
The upper cover substrate 30 generally has a relatively great thickness, which is generally around 400 μm, in order to meet process requirements. Therefore, the thickness of a chip package formed by cutting a packaged wafer is great, and the overall thickness of a subsequent module on the chip package is great as well, which cannot meet the market demand for thinner electronic products.
To reduce the thickness of the wafer package, the upper cover substrate on the surface of the packaged wafer is removed (as shown in FIG. 2) to expose the sensing region 20. In this case, although the thickness of the wafer package is reduced, the overall performance of the packaging structure is affected since the sensing region 20 is vulnerable to pollution and damage.
Therefore, there is a need for a packaging method which can reduce the thickness of the packaging structure without affecting the performance of the packaging structure.